Trap Generation in Whole Gate Stacks of FeFET With TiN/Hf0.5Zr0.5O2/SiOx/Si (MFIS) Gate Structure During Endurance Fatigue-Reference-Cited by-同舟云学术

Trap Generation in Whole Gate Stacks of FeFET With TiN/Hf_0.5Zr_0.5O₂/SiO_x/Si (MFIS) Gate Structure During Endurance Fatigue

Published:2022-12 Issue:12 Volume:69 Page:6547-6551
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Duan Jiahui¹^ORCID,Zhao Shujing¹^ORCID,Tian Fengbin¹^ORCID,Xiang Jinjuan²,Han Kai³^ORCID,Li Tingting¹,Xu Hao¹^ORCID,Wang Xiaolei¹^ORCID,Wang Wenwu¹,Ye Tianchun¹^ORCID

Affiliation:

1. Key Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China

2. Beijing Superstring Academy of Memory Technology, Beijing, China

3. School of Physics and Optoelectronic Engineering, Weifang University, Shandong, China

Funder

National Natural Science Foundation of China

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/16/9967813/09937151.pdf?arnumber=9937151

Reference32 articles.

1. Transient Charging and Discharging Behaviors of Border Traps in the Dual-Layer $\hbox{HfO}_{2}/\hbox{SiO}_{2}$ High- $\kappa$ Gate Stack Observed by Using Low-Frequency Charge Pumping Method

2. Border Traps in Ge/III–V Channel Devices: Analysis and Reliability Aspects

3. Low-Frequency Noise Assessment of Work Function Engineering Cap Layers in High-k Gate Stacks

4. Improved TDDB Reliability and Interface States in 5-nm Hf0.5Zr0.5O2 Ferroelectric Technologies Using NH3 Plasma and Microwave Annealing

5. Effects of Annealing on Ferroelectric Hafnium–Zirconium–Oxide-Based Transistor Technology

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