Novel Dual Liner Process for Side-Shielded Forksheet Device With Superior Design Margin

Author:

Kim Munhyeon1ORCID,Lee Kitae1ORCID,Kim Sihyun1ORCID,Lee Jong-Ho1ORCID,Park Byung-Gook1ORCID,Kwon Daewoong2ORCID

Affiliation:

1. Department of Electrical and Computer Engineering and the Inter-University Semiconductor Research Center, Seoul National University, Seoul, South Korea

2. Department of Electrical and Computer Engineering and the 3D Convergence Center, Inha University, Incheon, South Korea

Funder

Brain Korea 21 Four Program

Future Semiconductor Device Technology Development Program

Ministry of Trade, Industry and Energy (MOTIE) and Korea Semiconductor Research Consortium

Samsung Electronics Co., Ltd

National Research Foundation

Korean Ministry of Science and Information and Communications Technology

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Reference18 articles.

1. A Comprehensive Study of Nanosheet and Forksheet SRAM for Beyond N5 Node

2. Novel forksheet device architecture as ultimate logic scaling device towards 2nm;weckx;IEDM Tech Dig,2019

3. Economics of semiconductor scaling - a cost analysis for advanced technology node

4. Forksheet FETs for advanced CMOS scaling: Forksheet-nanosheet co-integration and dual work function metal gates at 17nm N-P space;mertens;Proc Symp VLSI Technol,2021

5. Process variation effect, metal-gate work-function fluctuation and random dopant fluctuation of 10-nm gate-all-around silicon nanowire MOSFET devices

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