A Comprehensive Study of Nanosheet and Forksheet SRAM for Beyond N5 Node
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/16/9493680/09464756.pdf?arnumber=9464756
Cited by 24 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Nanosized-Metal-Grain-Pattern-Dependent Threshold-Voltage Models for the Vertically Stacked Multichannel Gate-All-Around Si Nanosheet MOSFETs and Their Applications in Circuit Simulation;IEEE Transactions on Electron Devices;2024-01
2. A Novel Zigzag SRAM Bitcell Design in the Complementary FET Framework;IEEE Transactions on Electron Devices;2023-09
3. History of MOS Memory Evolution on DRAM and SRAM;75th Anniversary of the Transistor;2023-07-03
4. 3D SRAM Macro Design in 3D Nanofabric Process Technology;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-07
5. Performance and Stability Analysis of Built-In Self-Read and Write Assist 10T SRAM Cell;Active and Passive Electronic Components;2023-06-30
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