Impact of Process Variation on Nanosheet Gate-All-Around Complementary FET (CFET)
Author:
Affiliation:
1. Department of Electrical Engineering, East China Normal University, Shanghai, China
2. State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai, China
Funder
National Natural Science Foundation of China
Natural Science Foundation of Shanghai
Shanghai Science and Technology Innovation Action Plan
Shanghai Science and Technology Explorer Plan
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/16/9802454/09786007.pdf?arnumber=9786007
Reference39 articles.
1. Vertically Stacked Gate-All-Around Si Nanowire CMOS Transistors with Reduced Vertical Nanowires Separation, New Work Function Metal Gate Solutions, and DC/AC Performance Optimization
2. Investigation of Electrical Characteristic Behavior Induced by Channel-Release Process in Stacked Nanosheet Gate-All-Around MOSFETs
3. A Device-Level Characterization Approach to Quantify the Impacts of Different Random Variation Sources in FinFET Technology
4. Metal-Gate Granularity-Induced Threshold Voltage Variability and Mismatch in Si Gate-All-Around Nanowire n-MOSFETs
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1. Statistical analysis of vertically stacked nanosheet complementary FET based on polycrystalline silicon with multiple grain boundaries;Results in Physics;2024-08
2. Statistical Device Simulation and Machine Learning of Process Variation Effects of Vertically Stacked Gate-All-Around Si Nanosheet CFETs;IEEE Transactions on Nanotechnology;2024
3. Compact Model Build Upon Dynamic Weighting Artificial Neural Network Approach for Complementary Field Effect Transistors;IEEE Transactions on Electron Devices;2024-01
4. Vertically Stacked Nanosheet Number Optimization Strategy for Complementary FET (CFET) Scaling Beyond 2 nm;IEEE Transactions on Electron Devices;2023-12
5. Impact of Random Dipole Fluctuation-Induced Variation on Nanosheet Devices;IEEE Electron Device Letters;2023-10
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