A 91-dB DR 20-kHz BW 5th-Order Multi-Step Incremental ADC for Sensor Interfaces by Re-Using a MASH 2-1 Modulator
Author:
Affiliation:
1. National Yang Ming Chiao Tung University,Hsinchu,Taiwan
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9980472/9980536/09980590.pdf?arnumber=9980590
Reference6 articles.
1. A 1.1mW 200kS/s incremental ΔΣ ADC with a DR of 91.5dB using integrator slicing for dynamic power reduction
2. A 94.3-dB SFDR, 91.5-dB DR, and 200-kS/s CT Incremental Delta–Sigma Modulator With Differentially Reset FIR Feedback
3. A Hybrid Continuous Time Incremental and SAR Two-Step ADC with 90.5dB DR over 1MHz BW;wang;SSC-L,2022
4. A 0.9-V DAC-Calibration-Free Continuous-Time Incremental Delta–Sigma Modulator Achieving 97-dB SFDR at 2 MS/s in 28-nm CMOS
5. A 14b two fold time-interleaved incremental ?? ADC using hardware sharing;vogelmann;TCAS-I 2020,0
Cited by 3 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A 2-2 MASH ΔΣ ADC with fast-charge CLS input buffer and dual double sampling achieving 103.3-dB SNDR and ±2.5-ppm/FSR INL;Microelectronics Journal;2024-02
2. Design Examples;Incremental Data Converters for Sensor Interfaces;2023-11-03
3. A Multistep Multistage Fifth-Order Incremental Delta Sigma Analog-to-Digital Converter for Sensor Interfaces;IEEE Journal of Solid-State Circuits;2023-10
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