Test set compaction for combinational circuits-Reference-Cited by-同舟云学术

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Test set compaction for combinational circuits

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Container-title:Proceedings First Asian Test Symposium (ATS `92)
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Author:

Jau-Shien Chang ,Chen-Shang Lin

Publisher

IEEE Comput. Soc. Press

Link

http://xplorestaging.ieee.org/ielx2/436/5869/00224429.pdf?arnumber=224429

Cited by 21 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A fast test compaction method using dedicated Pure MaxSAT solver embedded in DFT flow;Integration;2025-01

2. A Static Test Compaction Method Based on GCN Assisted Fault Gate Classification;2024 IEEE International Test Conference in Asia (ITC-Asia);2024-08-18

3. A Fast Test Compaction Method for Commercial DFT Flow Using Dedicated Pure-MaxSAT Solver;2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC);2024-01-22

4. Dynamic Test Compaction of a Compressed Test Set Shared Among Logic Blocks;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2024-01

5. A Distributed ATPG System Combining Test Compaction Based on Pure MaxSAT;2023 IEEE 32nd Asian Test Symposium (ATS);2023-10-14

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