A Static Test Compaction Method Based on GCN Assisted Fault Gate Classification
Author:
Affiliation:
1. Chinese Academy of Sciences,State Key Lab of Processors, Institute of Computing Technology
2. University of Science and Technology Bejing
Funder
National Natural Science Foundation of China
Youth Innovation Promotion Association
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10661305/10661306/10661347.pdf?arnumber=10661347
Reference18 articles.
1. Compaction of ATPG-generated test sequences for sequential circuits
2. Two-Dimensional Static Test Compaction for Functional Test Sequences
3. A scalable method for the generation of small test sets
4. Test Set Generation with a Large Number of Unspecified Bits Using Static and Dynamic Techniques
5. On the generation of compact test sets
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