Analysis of FPGA SEU sensitivity to combined effects of conducted EMI and TID-Reference-Cited by-同舟云学术

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Analysis of FPGA SEU sensitivity to combined effects of conducted EMI and TID

Published:2016-05 Issue: Volume: Page:
ISSN:
Container-title:2016 Asia-Pacific International Symposium on Electromagnetic Compatibility (APEMC)
language:
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Author:

Benfica Juliano,Green Bruno,Porcher Bruno C.,Poehls Leticia Bolzani,Vargas Fabian,Medina Nilberto H.,Added Nemitala,de Aguiar Vitor A. P.,Macchione Eduardo L. A.,Aguirre Fernando,da Silveira Marcilei A. G.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7510516/7522714/07522900.pdf?arnumber=7522900

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Simulation and empirical validation of new sensitivity based reliability analysis technique for processors deployed in industrial drives;COMPEL - The international journal for computation and mathematics in electrical and electronic engineering;2022-10-05

2. A SHA-256 Hybrid-Redundancy Hardware Architecture for Detecting and Correcting Errors;Sensors;2022-07-03

3. An SHA-3 Hardware Architecture against Failures Based on Hamming Codes and Triple Modular Redundancy;Sensors;2022-04-13

4. Conducted EMI susceptibility analysis of a COTS processor as function of thermal cycling and overvoltage stresses;Microelectronics Reliability;2021-11

5. Hybrid Pipeline Hardware Architecture Based on Error Detection and Correction for AES;Sensors;2021-08-22

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