Design of Adiabatic Logic Two Tail Comparator for Low Power and Analyze with CMOS Comparator
Author:
Affiliation:
1. Saveetha University,Department of Electronics and Communication Engineering,Chennai,Tamilnadu,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10073967/10073974/10074436.pdf?arnumber=10074436
Reference17 articles.
1. Design of Low Power High Speed Double Tail Comparator using Power Gating Techniques
2. Design and Simulation of Low-Power ADC Using Double-Tail Comparator;konde,0
3. New improved high speed low power double tail comparator design for 2.5 GHz input signal
4. DESIGN OF ADIABATIC LOGIC BASED COMPARATOR FOR LOW POWER AND HIGH SPEED APPLICATIONS;samuel;ICTACT Journal on Microelectronics,2017
5. Adiabatic flip-flops and sequential circuit design using novel resettable adiabatic buffers
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