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Hermetic wafer level packaging of MEMS components using through silicon via and wafer to wafer bonding technologies

  • Published:2013-05 Issue: Volume: Page:
  • ISSN:
  • Container-title:2013 IEEE 63rd Electronic Components and Technology Conference
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Author:

Zoschke K.1,Manier C.-A.1,Wilke M.1,Jurgensen N.1,Oppermann H.1,Ruffieux D.2,Dekker J.3,Heikkinen Hannele3,Piazza S. Dalla4,Allegato G.5,Lang K.-D.6

Affiliation:

1. Fraunhofer IZM, Gustav-Meyer-Allee 25, 13355 Berlin

2. CSEM, SA Jaquet Droz 7, CH-2002 Neuchâtel, Switzerland

3. VTT Technical Research Centre of Finland, Tietotie 3, O2044 VTT, Espoo Finland

4. Micro Crystal AG, Muehlestrasse 14, CH-2540, Grenchen, Switzerland

5. STMicroelectronics, Via C. Olivetti 2, 20864, Agrate Brianza, Italy

6. Technical University of Berlin, Gustav-Meyer-Allee 25, 13355 Berlin

Publisher

IEEE

Cited by 11 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Ultrathin Glass-Based Wafer-Level Integration for Miniaturized Hermetic MEMS Application;IEEE Transactions on Components, Packaging and Manufacturing Technology;2023-01

2. Hermetic chip-scale packaging using Au:Sn eutectic bonding for implantable devices;Journal of Micromechanics and Microengineering;2021-07-26

3. Solder Joints in PCB Assembly and Semiconductor Packaging;Assembly and Reliability of Lead-Free Solder Joints;2020

4. Microsystems using three-dimensional integration and TSV technologies: Fundamentals and applications;Microelectronic Engineering;2019-04

5. Overview of Heterogeneous Integrations;Heterogeneous Integrations;2019
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