Bonding technologies for chip level and wafer level 3D integration-Reference-Cited by-同舟云学术

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Bonding technologies for chip level and wafer level 3D integration

Published:2014-05 Issue: Volume: Page:
ISSN:
Container-title:2014 IEEE 64th Electronic Components and Technology Conference (ECTC)
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Author:

Sakuma Katsuyuki,Skordas Spyridon,Zitz Jeffrey,Perfecto Eric,Guthrie William,Guerin Luc,Langlois Richard,Liu Hsichang,Ramachandran Koushik,Lin Wei,Winstel Kevin,Kohara Sayuri,Sueoka Kuniaki,Angyal Matthew,Graves-Abe Troy,Berger Daniel,Knickerbocker John,Iyer Subramanian

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/6884273/6897249/06897355.pdf?arnumber=6897355

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Functional Testing of AI Cores through Thinned 3D I/O Buffer Dies in 3D Die-Stacked Modules;2022 IEEE 72nd Electronic Components and Technology Conference (ECTC);2022-05

2. A Review of Recent Research on Heat Transfer in Three-Dimensional Integrated Circuits (3-D ICs);IEEE Transactions on Components, Packaging and Manufacturing Technology;2021-05

3. Die and Package Level Thermal and Thermal/Moisture Stresses in 3D Packaging: Modeling and Characterization;3D Microelectronic Packaging;2017

4. Oxide-Oxide Thermocompression Direct Bonding Technologies with Capillary Self-Assembly for Multichip-to-Wafer Heterogeneous 3D System Integration;Micromachines;2016-10-10

5. Three-Dimensional Dynamic Random Access Memories Using Through-Silicon-Vias;IEEE Journal on Emerging and Selected Topics in Circuits and Systems;2016-09

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