Innovative Design of Crackstop Wall for 14nm Technology Node and Beyond
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/8415930/8429093/08429587.pdf?arnumber=8429587
Cited by 9 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Limits for Dicing Speed Based on Crack Stop Constructions with Different Levels of Robustness;2024 IEEE 74th Electronic Components and Technology Conference (ECTC);2024-05-28
2. Microcracking in On-Chip Interconnect Stacks: FEM Simulation and Concept for Fatigue Test;Journal of Electronic Materials;2024-05-09
3. Crack Stop as a Coupling Element Between an IC Chip and Antenna;2024 18th European Conference on Antennas and Propagation (EuCAP);2024-03-17
4. Minimizing die fracture in 3DIC die integration;Journal of Micro/Nanopatterning, Materials, and Metrology;2024-01-02
5. Implementation of New Robustness Assessment Methodology for Crack Stop Constructions;2023 IEEE 73rd Electronic Components and Technology Conference (ECTC);2023-05
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