Sensitivity to soft errors of NMOS and PMOS transistors evaluated by latches with stacking structures in a 65 nm FDSOI process-Reference-Cited by-同舟云学术

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Sensitivity to soft errors of NMOS and PMOS transistors evaluated by latches with stacking structures in a 65 nm FDSOI process

Published:2018-03 Issue: Volume: Page:
ISSN:
Container-title:2018 IEEE International Reliability Physics Symposium (IRPS)
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Author:

Yamada Kodai,Maruoka Haruki,Furuta Jun,Kobayashi Kazutoshi

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8345372/8353529/08353691.pdf?arnumber=8353691

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Soft-Error Tolerance by Guard-Gate Structures on Flip-Flops in 22 and 65 nm FD-SOI Technologies;IEICE Transactions on Electronics;2024-07-01

2. SEU Sensitivity of PMOS and NMOS Transistors in a 65 nm Bulk Process by α-Particle Irradiation;2023 International Conference on IC Design and Technology (ICICDT);2023-09-25

3. Radiation Hardness Evaluations of a Stacked Flip Flop in a 22 nm FD-SOI Process by Heavy-Ion Irradiation;2023 IEEE 29th International Symposium on On-Line Testing and Robust System Design (IOLTS);2023-07-03

4. Soft-error Tolerance by Guard-Gate Structures on Flip-Flops in 22/65 nm FD-SOI Technologies;2022 22nd European Conference on Radiation and Its Effects on Components and Systems (RADECS);2022-10-03

5. Energy-efficient and Reliable Inference in Nonvolatile Memory under Extreme Operating Conditions;ACM Transactions on Embedded Computing Systems;2022-09-30

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