Soft-Error Tolerance by Guard-Gate Structures on Flip-Flops in 22 and 65 nm FD-SOI Technologies-Reference-Cited by-同舟云学术

Soft-Error Tolerance by Guard-Gate Structures on Flip-Flops in 22 and 65 nm FD-SOI Technologies

Published:2024-07-01 Issue:7 Volume:E107.C Page:191-200
ISSN:0916-8524
Container-title:IEICE Transactions on Electronics
language:en
Short-container-title:IEICE Trans. Electron.

Author:

NAKAJIMA Ryuichi¹,ITO Takafumi¹,SUGITANI Shotaro¹,KII Tomoya¹,EBARA Mitsunori¹,FURUTA Jun¹,KOBAYASHI Kazutoshi¹,LOUVAT Mathieu²,JACQUET Francois²,ELOY Jean-Christophe²,MONTFORT Olivier²,JURE Lionel²,HUARD Vincent²

Affiliation:

1. Graduate School of Science and Technology, Kyoto Institute of Technology

2. Dolphin Design

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Link

https://www.jstage.jst.go.jp/article/transele/E107.C/7/E107.C_2023CDP0004/_pdf

Reference31 articles.

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