A Framework for Practical Design of Switching Nodes with Parallel-Connected MOSFETs
Author:
Affiliation:
1. McMaster University,McMaster Automotive Resource Centre (MARC),Hamilton,ON,Canada
2. Eaton Research Labs,Menomonee Falls,WI,USA
3. Eaton Corporation,Aerospace Group, Fluid and Electrical Distribution Division,Torrance,CA,USA
Funder
CMC Microsystems
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9813698/9813746/09813977.pdf?arnumber=9813977
Reference16 articles.
1. Mosfet power losses and how they affect power-supply efficiency;lakkas;Texas Instruments Analog Applicat J,2016
2. Apt0103 - making use of gate charge information in mosfet and igbt data sheets;mcarthur;Advanced power technology,2016
3. Mosfet power losses calculation using the datasheet parameters;graovac;Infineon Technologies AG,2006
4. Influence of Parasitic Inductances on Switching Performance of SiC MOSFET
5. Research of PCB Parasitic Inductance in the GaN Transistor Power Loop
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