Towards an ADC BIST scheme using the histogram test technique-Reference-Cited by-同舟云学术

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Towards an ADC BIST scheme using the histogram test technique

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Container-title:Proceedings IEEE European Test Workshop
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Author:

Azais F.,Bernard S.,Betrand Y.,Renovell M.

Publisher

IEEE Comput. Soc

Link

http://xplorestaging.ieee.org/ielx5/7017/18915/00873779.pdf?arnumber=873779

Cited by 29 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. An On Chip BIST Architecture for ADC Parameter Testing and Measurement;2024 1st International Conference on Innovative Sustainable Technologies for Energy, Mechatronics, and Smart Systems (ISTEMS);2024-04-26

2. Digital Non-Linearity Calibration for ADCs With Redundancy Using a New LUT Approach;IEEE Transactions on Circuits and Systems I: Regular Papers;2021-08

3. Frequency and Amplitude Domain DAC-ADC Co-Testing Using Ternary Signals;IEEE Transactions on Instrumentation and Measurement;2020-07

4. Black-Box Calibration for ADCs With Hard Nonlinear Errors Using a Novel INL-Based Additive Code: A Pipeline ADC Case Study;IEEE Transactions on Circuits and Systems I: Regular Papers;2017-07

5. Histogram-Based Calibration Method for Pipeline ADCs;PLOS ONE;2015-06-12

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