Digital Non-Linearity Calibration for ADCs With Redundancy Using a New LUT Approach
Author:
Funder
Spanish Government
European FEDER Program
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8919/9481308/09394592.pdf?arnumber=9394592
Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Behavioral Model for High-Speed SAR ADCs With On-Chip References;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-12
2. LIORAT: NN Layer I/O Range Training for Area/Energy-Efficient Low-Bit A/D Conversion System Design in Error-Tolerant Computation-in-Memory;2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD);2023-10-28
3. An offset and gain error calibration method in high-precision SAR ADCs;Microelectronics Journal;2023-09
4. A Histogram-Based Digital Background Calibration Technique for Pipelined A/D Converters;2022 Iranian International Conference on Microelectronics (IICM);2022-12-20
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