Behavioral Model for High-Speed SAR ADCs With On-Chip References
Author:
Affiliation:
1. Instituto de Microelectrónica de Sevilla (IMSE-CNM), Universidad de Sevilla, CSIC, Seville, Spain
2. Instituto Universitario de Investigación en Ingeniería de Aragón (I3A), Universidad de Zaragoza, Zaragoza, Spain
Funder
Spanish Government
European FEDER (Fondo Europeo de Desarrollo Regional) program
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Link
http://xplorestaging.ieee.org/ielx7/92/10328903/10278146.pdf?arnumber=10278146
Reference29 articles.
1. Description of SAR ADCs with Digital Redundancy using a Unified Hardware-Based Approach
2. A 0.003 mm$^{2}$ 10 b 240 MS/s 0.7 mW SAR ADC in 28 nm CMOS With Digital Error Correction and Correlated-Reversed Switching
3. A SAR ADC with Reconfigurable Delay and Redundancy to Relax the Reference Driver
4. Redundant SAR ADCs with Split-capacitor DAC
5. A 12-bit, 45-MS/s, 3-mW Redundant Successive-Approximation-Register Analog-to-Digital Converter With Digital Calibration
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