Robust multi-VT 4T SRAM cell in 45nm thin BOx fully-depleted SOI technology with ground plane
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IEEE
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http://xplorestaging.ieee.org/ielx5/5159181/5166240/05166293.pdf?arnumber=5166293
Cited by 3 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Low power CMOS based Self Controlled Precharge Free Content Addressable Memory with Minimum area for Image Processing Devices;International Journal of Systems Applications, Engineering & Development;2020-12-21
2. Energy-Efficient 4T SRAM Bitcell with 2T Read-Port for Ultra-Low-Voltage Operations in 28 nm 3D Monolithic CoolCubeTM Technology;Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures;2018-07-17
3. High-Density 4T SRAM Bitcell in 14-nm 3-D CoolCube Technology Exploiting Assist Techniques;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2017-08
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