Energy-Efficient 4T SRAM Bitcell with 2T Read-Port for Ultra-Low-Voltage Operations in 28 nm 3D Monolithic CoolCubeTM Technology-Reference-Cited by-同舟云学术

Energy-Efficient 4T SRAM Bitcell with 2T Read-Port for Ultra-Low-Voltage Operations in 28 nm 3D Monolithic CoolCubeTM Technology

Published:2018-07-17 Issue: Volume: Page:
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Container-title:Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures
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Author:

Boumchedda Reda¹,Noel Jean-Philippe²,Giraud Bastien²,Makosiej Adam²,Rios Marco Antonio²,Esmanhotto Eduardo²,Bourde-Cicé Emilien²,Bellet Mathis²,Turgis David³,Beigne Edith²

Affiliation:

1. STMicroelectronics, Crolles, France, Univ. Grenoble Alpes CEA, LETI, MINATEC Campus, Grenoble, France

2. Univ. Grenoble Alpes, CEA, LETI, MINATEC Campus, Grenoble, France

3. STMicroelectronis, Crolles, France

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3232195.3232210

Reference16 articles.

1. V. Kumar etal "A Sub-0.5V Reliability Aware-Negative Bitline Write-Assisted 8T DP-SRAM and WL Strapping Novel Architecture to Counter Dual Patterning Issues in 10nm FinFET " VLSID pp. 269--274 2017. V. Kumar et al. "A Sub-0.5V Reliability Aware-Negative Bitline Write-Assisted 8T DP-SRAM and WL Strapping Novel Architecture to Counter Dual Patterning Issues in 10nm FinFET " VLSID pp. 269--274 2017.

2. E. Karl etal "A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry " ISSCC pp. 230--232 2012. E. Karl et al. "A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry " ISSCC pp. 230--232 2012.

3. S. Kumar etal "SRAM write assist techniques for low power applications " ICSC pp. 425--430 2016. S. Kumar et al. "SRAM write assist techniques for low power applications " ICSC pp. 425--430 2016.

4. J.-P. Noel etal "Robust multi-VT 4T SRAM cell in 45nm thin BOx fully-depleted SOI technology with ground plane " ICICDT pp. 191--194 2009. J.-P. Noel et al. "Robust multi-VT 4T SRAM cell in 45nm thin BOx fully-depleted SOI technology with ground plane " ICICDT pp. 191--194 2009.

5. V. Asthana etal "Circuit optimization of 4T 6T 8T 10T SRAM bitcells in 28nm UTBB FD-SOI technology using back-gate bias control " ESSCIRC pp. 415--418 2013. V. Asthana et al. "Circuit optimization of 4T 6T 8T 10T SRAM bitcells in 28nm UTBB FD-SOI technology using back-gate bias control " ESSCIRC pp. 415--418 2013.