A Sub-0.5V Reliability Aware-Negative Bitline Write-Assisted 8T DP-SRAM and WL Strapping Novel Architecture to Counter Dual Patterning Issues in 10nm FinFET
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/7880094/7884715/07884790.pdf?arnumber=7884790
Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
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2. Analysis of Word Line Shaping Techniques for In-Memory Computing in SRAMs;2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS);2021-11-28
3. Area Efficient & High Performance Word Line Segmented Architecture in 7nm FinFET SRAM Compiler;2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID);2019-01
4. Energy-Efficient 4T SRAM Bitcell with 2T Read-Port for Ultra-Low-Voltage Operations in 28 nm 3D Monolithic CoolCubeTM Technology;Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures;2018-07-17
5. Self-Timed Shaper Circuit for Wide Memories in Advanced CMOS Technologies;2018 IEEE International Symposium on Circuits and Systems (ISCAS);2018-05
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