Area Efficient & High Performance Word Line Segmented Architecture in 7nm FinFET SRAM Compiler-Reference-Cited by-同舟云学术

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Area Efficient & High Performance Word Line Segmented Architecture in 7nm FinFET SRAM Compiler

Published:2019-01 Issue: Volume: Page:
ISSN:
Container-title:2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID)
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Author:

Kumar Vinay,Kapoor Neeraj,Kumar Sudhir,Juneja Monila,Khanuja Amit

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8698529/8710751/08711139.pdf?arnumber=8711139

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 4.13-GHz UHS Pseudo Two-Port SRAM With BL Charge Time Reduction and Flying Word-Line for HPC Applications in 4-nm FinFET Technology;IEEE Journal of Solid-State Circuits;2024-04

2. ARBiS: A Hardware-Efficient SRAM CIM CNN Accelerator With Cyclic-Shift Weight Duplication and Parasitic-Capacitance Charge Sharing for AI Edge Application;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-01

3. Analysis of Word Line Shaping Techniques for In-Memory Computing in SRAMs;2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS);2021-11-28

4. Hazardous heavy metals contamination of vegetables and food chain: Role of sustainable remediation approaches - A review;Environmental Research;2019-12

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