Author:
Waris Haroon,Wang Chenghua,Liu Weiqiang,Lombardi Fabrizio
Cited by
12 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Integrated MAC-based Systolic Arrays: Design and Performance Evaluation;Proceedings of the Great Lakes Symposium on VLSI 2024;2024-06-12
2. PSO Optimized Design of Error Balanced Weight Stationary Systolic Array Architecture for CNN;2024 25th International Symposium on Quality Electronic Design (ISQED);2024-04-03
3. Performance-Aware Design of Approximate Integrated MAC Factored Systolic Array Accelerators;2024 25th International Symposium on Quality Electronic Design (ISQED);2024-04-03
4. OEDASA: Optimization Enabled Error-Diluted Approximate Systolic Array Design for an Image Processing Application;2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID);2024-01-06
5. Design-Space Exploration of Systolic Array for Edge Inferencing Applications;The Third International Conference on Artificial Intelligence and Machine Learning Systems;2023-10-25