Design-Space Exploration of Systolic Array for Edge Inferencing Applications

Author:

H C Prashanth1ORCID,Mogal Yash Dharmesh1ORCID,Rao Madhav2ORCID

Affiliation:

1. International Institute of Information Technology Bangalore, IN

2. International Institute of information Technology, Bangalore, IN

Publisher

ACM

Reference37 articles.

1. Hazoor Ahmad, Muhammad Tanvir, Muhammad Abdullah, Muhammad Usama Javed, Rehan Hafiz, and Muhammad Shafique. 2019. Systimator: A Design Space Exploration Methodology for Systolic Array based CNNs Acceleration on the FPGA-based Edge Nodes. CoRR abs/1901.04986 (2019). http://arxiv.org/abs/1901.04986

2. Multi-level Stress Assessment Using Multi-domain Fusion of ECG Signal

3. HardCompress: A Novel Hardware-based Low-power Compression Scheme for DNN Accelerators

4. A Novel Low-Power Compression Scheme for Systolic Array-Based Deep Learning Accelerators

5. A Real-Time Architecture for Pruning the Effectual Computations in Deep Neural Networks

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