An Automated Synthesis Framework for Fast Evaluation of Maximum Operating Frequency-Reference-Cited by-同舟云学术

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An Automated Synthesis Framework for Fast Evaluation of Maximum Operating Frequency

Published:2023-02-05 Issue: Volume: Page:
ISSN:
Container-title:2023 International Conference on Electronics, Information, and Communication (ICEIC)
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Author:

Kong Byeong Yong¹,Yoo Hoyoung²,Lee Youngjoo³

Affiliation:

1. Kongju National University,Division of Electrical, Electronic, and Control Engineering,Cheonan,South Korea

2. Chungnam National University,Department of Electronics Engineering,Daejeon,South Korea

3. Pohang University of Science and Technology (POSTECH),Department of Electrical Engineering,Pohang,South Korea

Funder

National Research Foundation

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10049840/10049805/10049896.pdf?arnumber=10049896

Reference11 articles.

1. A General Logic Synthesis Framework for Memristor-based Logic Design

2. Logic synthesis speeds ASIC design

3. Logic Synthesis of Approximate Circuits

4. Tutorial: Design of a logic synthesis system;rudell;Proc Des Autom Conf (DAC),1996

5. Ternary Logic Synthesis with Modified Quine-McCluskey Algorithm

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