Author:
Zhu Zhenhua,Ma Mingyuan,Liu Jialong,Xu Liying,Chen Xiaoming,Yang Yuchao,Wang Yu,Yang Huazhong
Cited by
9 articles.
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1. Integrated Netlist Synthesis and In-Memory Mapping for Memristor-Aided Logic;Proceedings of the Great Lakes Symposium on VLSI 2024;2024-06-12
2. A Topology-flattening-based Automated Incremental Synthesis Method;2024 2nd International Symposium of Electronics Design Automation (ISEDA);2024-05-10
3. LOSSS-Logic Synthesis based on Several Stateful logic gates for high time-efficient computing;2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC);2024-01-22
4. An Automated Synthesis Framework for Fast Evaluation of Maximum Operating Frequency;2023 International Conference on Electronics, Information, and Communication (ICEIC);2023-02-05
5. Design and Simulation of Peripheral Driving Circuitry for Computational ReRAM;2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS);2022-11-16