Device Simulation Based Machine Learning Technique for III V TFET-Reference-Cited by-同舟云学术

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Device Simulation Based Machine Learning Technique for III V TFET

Published:2024-04-17 Issue: Volume: Page:1-6
ISSN:
Container-title:2024 International Conference on Recent Advances in Electrical, Electronics, Ubiquitous Communication, and Computational Intelligence (RAEEUCCI)
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Author:

Saravanan M¹,Parthasarathy Eswaran²,Ajayan J³,Rahi Shiromani Balmukund⁴

Affiliation:

1. Sri Eshwar College of Engineering,Department of ECE,Coimbatore,India

2. SRM Institute of Science and Technology,Department of ECE,Chennai,India

3. SR University,Department of ECE,Warangal,Telangana,India

4. University School of Information and Communication Technology, Gautam Buddha University,Greater Noida,Uttar Pradesh

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx8/10547720/10547724/10547980.pdf?arnumber=10547980

Reference19 articles.

1. Investigation of impact of gate underlap/overlap on the analog/RF performance of composite channel double gate MOSFETs

2. A review of III-V Tunnel Field Effect Transistors for future ultra low power digital/analog applications

3. LG = 20 nm High Performance GaAs Substrate Based Metamorphic Metal Oxide Semiconductor High Electron Mobility Transistor for Next Generation High Speed Low Power Applications

4. Impact of Pocket Layer on Linearity and Analog/RF Performance of InAs-GaSb Vertical Tunnel Field-Effect Transistor

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