Synthesis of VHDL code for FPGA design flow using Xilinx PlanAhead tool-Reference-Cited by-同舟云学术

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Synthesis of VHDL code for FPGA design flow using Xilinx PlanAhead tool

Published:2012-07 Issue: Volume: Page:
ISSN:
Container-title:International Conference on Education and e-Learning Innovations
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Author:

Sarker Md. Abdul Latif,Lee Moon Ho

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/6353667/6360561/06360614.pdf?arnumber=6360614

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Logic locking emulator on FPGA: A conceptual view;2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID);2024-01-06

2. Implementation of Single-Phase ZSI with LC Filter for PV Applications;Lecture Notes in Electrical Engineering;2023

3. FPGA Virtualization Mechanism Based on Heterogeneous Zynq Platforms;Journal of Circuits, Systems and Computers;2019-11

4. Introduction;Reconfigurable Cryptographic Processor;2018

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