29.3 A 14b 1GS/s RF sampling pipelined ADC with background calibration-Reference-Cited by-同舟云学术

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29.3 A 14b 1GS/s RF sampling pipelined ADC with background calibration

Published:2014-02 Issue: Volume: Page:
ISSN:
Container-title:2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)
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Author:

Ali Ahmed M. A.,Dinc Huseyin,Bhoraskar Paritosh,Dillon Chris,Puckett Scott,Gray Bryce,Speir Carroll,Lanford Jonathan,Jarman David,Brunsilius Janet,Derounian Peter,Jeffries Brad,Mehta Ushma,McShea Matt,Lee Ho-Young

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/6747109/6757318/06757522.pdf?arnumber=6757522

Cited by 17 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Fast and Cost-Effective Calibration Strategy of Inter-Stage Residual Amplification Errors for Cyclic-Pipelined ADCs;Electronics;2024-06-19

2. A 1.5GS/s Single-Channel Pipelined ADC With Large Dither Technique;2023 8th International Conference on Integrated Circuits and Microsystems (ICICM);2023-10-20

3. 2nd-Order shaping technique of the DAC mismatch error in noise shaping SAR ADCs;Analog Integrated Circuits and Signal Processing;2019-12-16

4. A Time-Interleaved 14-bit 500MS/s Charge-Domain ADC with Mix-signal Mismatch Calibration;2019 IEEE 4th International Conference on Integrated Circuits and Microsystems (ICICM);2019-10

5. High Precision Mix‐Signal Capacitor Mismatch Error Calibration Method for Charge‐Domain Pipelined ADC;Chinese Journal of Electronics;2019-03

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