2nd-Order shaping technique of the DAC mismatch error in noise shaping SAR ADCs-Reference-Cited by-同舟云学术

2nd-Order shaping technique of the DAC mismatch error in noise shaping SAR ADCs

Published:2019-12-16 Issue:1 Volume:102 Page:265-271
ISSN:0925-1030
Container-title:Analog Integrated Circuits and Signal Processing
language:en
Short-container-title:Analog Integr Circ Sig Process

Author:

Wang Peng,Sun Jie^ORCID

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Link

http://link.springer.com/content/pdf/10.1007/s10470-019-01572-1.pdf

Reference16 articles.

1. Liu, C.-C., et al. (2010). A 10b 100 MS/s 1.13 mW SAR ADC with binary-scaled error compensation. In Proceedings of IEEE ISSCC (pp. 386–387).

2. Liu, W., Huang, P., & Chiu, Y. (2011). A 12-bit, 45-MS/s, 3-mW redundant successive-approximation-register analog-to-digital converter with digital calibration. IEEE Journal of Solid-State Circuits,46(11), 2661–2672.

3. Hsieh, S., & Hsieh, C. (2016). A 0.3-V 0.705-fJ/conversion-step 10-bit SAR ADC with a shifted monotonic switching procedure in 90-nm CMOS. IEEE Transactions on Circuits and Systems II: Express Briefs,63(12), 1171–1175.

4. Liu, C. C., & Huang, M. (2017). A 0.46 mW 5 MHz-BW 79.7 dB-SNDR noise-shaping SAR ADC with dynamic-amplifier-based FIR–IIR filter. In Proceedings of IEEE ISSCC (pp. 466–467).

5. Guo, W., Zhuang, H., & Sun, N. (2017). A 13b-ENOB 173 dB-FoM 2nd-order NS SAR ADC with passive integrators. In Proceedings of IEEE VLSI (pp. C236–C237).

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