Author:
Wendel D.,Kalla R.,Cargoni R.,Clables J.,Friedrich J.,Frech R.,Kahle J.,Sinharoy B.,Starke W.,Taylor S.,Weitzel S.,Chu S.G.,Islam S.,Zyuban V.
Cited by
27 articles.
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1. A novel low power hybrid cache using GC-EDRAM cells;Integration;2021-11
2. Performance and Energy-Efficient Design of STT-RAM Last-Level Cache;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2018-06
3. A Survey of Low Power Design Techniques for Last Level Caches;Applied Reconfigurable Computing. Architectures, Tools, and Applications;2018
4. Efficient Timestamp-Based Cache Coherence Protocol for Many-Core Architectures;Proceedings of the 2016 International Conference on Supercomputing;2016-06
5. Architecting On-Chip DRAM Cache for Simultaneous Miss Rate and Latency Reduction;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2016-04