Efficient Timestamp-Based Cache Coherence Protocol for Many-Core Architectures
Author:
Affiliation:
1. College of Computer Science and Technology, Zhejiang University
2. School of Computing, National University of Singapore
3. Huawei Singapore Research Centre
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/2925426.2926270
Reference39 articles.
1. Why on-chip cache coherence is here to stay
2. D. J. Sorin M. D. Hill and D. A. Wood "A Primer on Memory Consistency and Cache Coherence " Morgan and Claypool Publishers 2011. D. J. Sorin M. D. Hill and D. A. Wood "A Primer on Memory Consistency and Cache Coherence " Morgan and Claypool Publishers 2011.
3. A. Gupta W.-D. Weber and T. Mowry "Reducing Memory and Traffic Requirements for Scalable Directory-Based Cache Coherence Schemes. " in International Conference for Parallel Processing 1990. A. Gupta W.-D. Weber and T. Mowry "Reducing Memory and Traffic Requirements for Scalable Directory-Based Cache Coherence Schemes. " in International Conference for Parallel Processing 1990.
4. SPACE
5. Spatiotemporal Coherence Tracking
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1. G-TSC: Timestamp Based Coherence for GPUs;2018 IEEE International Symposium on High Performance Computer Architecture (HPCA);2018-02
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