17.7 A digital DLL with hybrid DCC using 2-step duty error extraction and 180° phase aligner for 2.67Gb/S/pin 16Gb 4-H stack DDR4 SDRAM with TSVs-Reference-Cited by-同舟云学术

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17.7 A digital DLL with hybrid DCC using 2-step duty error extraction and 180° phase aligner for 2.67Gb/S/pin 16Gb 4-H stack DDR4 SDRAM with TSVs

Published:2015-02 Issue: Volume: Page:
ISSN:
Container-title:2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers
language:
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Author:

Yun Won-Joo,Song Indal,Jeoung Hanki,Choi Hundae,Lee Seok-Ho,Kim Jun-Bae,Kim Chi-Wook,Choi Jung-Hwan,Jang Seong-Jin,Choi Joo Sun

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7054075/7062838/07063056.pdf?arnumber=7063056

Cited by 14 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A shared TDC-based fast-lock all-digital DLL using a DCC-embedded delay line;Microelectronics Journal;2024-07

2. A 60-Gb/s 1.2-pJ/bit 1/4-Rate PAM-4 Receiver With a Jitter Compensation CDR;IEEE Journal of Solid-State Circuits;2024-02

3. A Design of a Dual Delay Line DLL with Wide Input Duty Cycle Range;Electronics;2023-06-16

4. A 0.8-3.5 GHz Shared TDC-Based Fast-Lock All-Digital DLL with a Built-in DCC;2021 IEEE International Symposium on Circuits and Systems (ISCAS);2021-05

5. 30-Gb/s 1.11-pJ/bit Single-Ended PAM-3 Transceiver for High-Speed Memory Links;IEEE Journal of Solid-State Circuits;2021-02

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