A Sub-200mV 6T SRAM in 0.13μm CMOS
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx5/4242240/4242241/04242400.pdf?arnumber=4242400
Cited by 11 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Reducing SRAM Reading Power With Column Data Segment and Weights Correlation Enhancement for CNN Processing;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2021-11
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3. On-Chip Cache Architecture Exploiting Hybrid Memory Structures for Near-Threshold Computing;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2019-12-01
4. 39% access time improvement, 11% energy reduction, 32 kbit 1-read/1-write 2-port static random-access memory using two-stage read boost and write-boost after read sensing scheme;Japanese Journal of Applied Physics;2016-03-23
5. Closed-form analytical model of static noise margin for ultra-low voltage eight-transistor tunnel FET static random access memory;Japanese Journal of Applied Physics;2016-03-07
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