On-Chip Cache Architecture Exploiting Hybrid Memory Structures for Near-Threshold Computing
Author:
Affiliation:
1. Kyoto University
2. Nagoya University
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing
Link
https://www.jstage.jst.go.jp/article/transfun/E102.A/12/E102.A_1741/_pdf
Reference20 articles.
1. [1] H. Xu, J. Shiomi, T. Ishihara, and H. Onodera, “Maximizing energy efficiency of on-chip caches exploiting hybrid memory structure,” 2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), pp.237-242, IEEE, July 2018. 10.1109/patmos.2018.8464141
2. [2] E.F. Nakamura, A.A.F. Loureiro, and A.C. Frery, “Information fusion for wireless sensor networks: Methods, models, and classifications,” ACM Comput. Surv., vol.39, no.3, pp.33-43, 2007. 10.1145/1267070.1267073
3. [3] S. Mittal, “A survey of architectural techniques for improving cache power efficiency,” Sustainable Computing: Informatics and Systems, vol.4, no.1, pp.33-43, Nov. 2013. 10.1016/j.suscom.2013.11.001
4. [4] D. Nagle, R. Uhlig, T.M. Mudge, and S. Sechrest, “Optimal allocation of on-chip memory for multiple-API operating systems,” ISCA'94 Proc. 21st Annual International Symposium on Computer Architecture, pp.358-369, IEEE, 1994. 10.1109/isca.1994.288135
5. [5] J.M. Mulder, N.T. Quach, and M.J. Flynn, “An area model for on-chip memories and its application,” J. Solid-State Circuits, vol.26, no.2, pp.98-106, Feb. 1991. 10.1109/4.68123
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