39% access time improvement, 11% energy reduction, 32 kbit 1-read/1-write 2-port static random-access memory using two-stage read boost and write-boost after read sensing scheme
Author:
Publisher
IOP Publishing
Subject
General Physics and Astronomy,Physics and Astronomy (miscellaneous),General Engineering
Link
http://stacks.iop.org/1347-4065/55/i=4S/a=04EF13/pdf
Reference35 articles.
1. A 6-ns 4-mb Cmos Sram With Offset-voltage-insensitive Current Sense Amplifiers
2. Driving source-line (DSL) cell architecture for sub-1-V high-speed low-power applications
3. A deep sub-V, single power-supply SRAM cell with multi-V/sub T/, boosted storage node and dynamic load
4. A read-static-noise-margin-free SRAM cell for low-V/sub dd/ and high-speed applications
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