Spur-free all-digital PLL in 65nm for mobile phones-Reference-Cited by-同舟云学术

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Spur-free all-digital PLL in 65nm for mobile phones

Published:2011-02 Issue: Volume: Page:
ISSN:
Container-title:2011 IEEE International Solid-State Circuits Conference
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Author:

Staszewski Robert Bogdan,Waheed Khurram,Vemulapalli Sudheer,Dulger Fikret,Wallberg John,Hung Chih-Ming,Eliezer Oren

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/5740653/5746170/05746215.pdf?arnumber=5746215

Cited by 19 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A High-Speed and Fully Symmetric Time-to-Digital Converter with Picosecond Resolution;2022 10th International Symposium on Next-Generation Electronics (ISNE);2023-05-12

2. A 31-$\mu$ W, 148-fs Step, 9-bit Capacitor-DAC-Based Constant-Slope Digital-to-Time Converter in 28-nm CMOS;IEEE Journal of Solid-State Circuits;2019-11

3. Structure of All-Digital Frequency Synthesiser for IoT and IoV Applications;Electronics;2018-12-27

4. A standard cell phase locked loop design, analysis and high-level synthesis tool (CellPLL);Integration;2017-06

5. All-digital pulse-expansion-based CMOS digital-to-time converter;Review of Scientific Instruments;2017-02

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