A 31-$\mu$ W, 148-fs Step, 9-bit Capacitor-DAC-Based Constant-Slope Digital-to-Time Converter in 28-nm CMOS-Reference-Cited by-同舟云学术

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A 31-$\mu$ W, 148-fs Step, 9-bit Capacitor-DAC-Based Constant-Slope Digital-to-Time Converter in 28-nm CMOS

Published:2019-11 Issue:11 Volume:54 Page:3075-3085
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Chen Peng^ORCID,Zhang Feifei,Zong Zhirui^ORCID,Hu Suoping^ORCID,Siriburanon Teerachot^ORCID,Staszewski Robert Bogdan^ORCID

Funder

Science Foundation Ireland

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/8880462/08850049.pdf?arnumber=8850049

Cited by 25 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Fractional-N Sampling PLL With a Merged Constant-Slope DTC and Sampling PD;IEEE Journal of Solid-State Circuits;2024-08

2. Analysis of a Split-Constant-Slope Digital-to-Time Converter Topology;2024 19th Conference on Ph.D Research in Microelectronics and Electronics (PRIME);2024-06-09

3. High precision low jitter pulse generator implemented with FPGA transceiver;Measurement;2024-05

4. A 10-bit 563-fs Step Constant-Slope Digital-to-Time Converter in 40-nm CMOS With Nonlinearity Cancellation and Range Extension Techniques;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-02

5. A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering;IEEE Journal of Solid-State Circuits;2023-12

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