16.5 An 8GS/s time-interleaved SAR ADC with unresolved decision detection achieving −58dBFS noise and 4GHz bandwidth in 28nm CMOS-Reference-Cited by-同舟云学术

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16.5 An 8GS/s time-interleaved SAR ADC with unresolved decision detection achieving −58dBFS noise and 4GHz bandwidth in 28nm CMOS

Published:2017-02 Issue: Volume: Page:
ISSN:
Container-title:2017 IEEE International Solid-State Circuits Conference (ISSCC)
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Author:

Keane John P.,Guilar Nathaniel J.,Stepanovic Dusan,Wuppermann Bernd,Wu Charles,Tsang Cheongyuen W.,Neff Robert,Nishimura Ken

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7866667/7870233/07870372.pdf?arnumber=7870372

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3. Design Methodology for Compact Single-Channel 3-Stage Capacitor-Array-Assisted Charge-Injection DAC-Based SAR ADC;IEEE Transactions on Circuits and Systems I: Regular Papers;2024

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5. A 10b 700 MS/s Single-Channel 1b/Cycle SAR ADC Using a Monotonic-Specific Feedback SAR Logic With Power-Delay-Optimized Unbalanced N/P-MOS Sizing;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-12

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