16.4 A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with background offset calibration-Reference-Cited by-同舟云学术

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16.4 A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with background offset calibration

Published:2017-02 Issue: Volume: Page:
ISSN:
Container-title:2017 IEEE International Solid-State Circuits Conference (ISSCC)
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Author:

Chan Chi-Hang,Zhu Yan,Ho Iok-Meng,Zhang Wai-Hong,U Seng-Pan,Martins Rui Paulo

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7866667/7870233/07870371.pdf?arnumber=7870371

Cited by 27 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 600MS/s 10-bit SAR ADC with unit via-based delta-length C-DAC in 22nm FDSOI;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

2. Design Methodology for Compact Single-Channel 3-Stage Capacitor-Array-Assisted Charge-Injection DAC-Based SAR ADC;IEEE Transactions on Circuits and Systems I: Regular Papers;2024

3. A 52.5-dB 2× Time-Interleaved 2.8-GS/s SAR ADC With 5-bit/Cycle Time-Domain Quantization and a Compact Signal DAC;IEEE Journal of Solid-State Circuits;2023-12

4. A 0.000261 mm² Single-Channel 1 GS/s 8-Bit 3-Stage Capacitor Array-Assisted Charge-Injection DAC-Based SAR ADC in 28 nm CMOS;2023 IEEE Asian Solid-State Circuits Conference (A-SSCC);2023-11-05

5. A VTC/TDC-Assisted 4× Interleaved 3.8 GS/s 7b 6.0 mW SAR ADC With 13 GHz ERBW;IEEE Journal of Solid-State Circuits;2023-04

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