A 0.000261 mm<sup>2</sup> Single-Channel 1 GS/s 8-Bit 3-Stage Capacitor Array-Assisted Charge-Injection DAC-Based SAR ADC in 28 nm CMOS-Reference-Cited by-同舟云学术

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A 0.000261 mm² Single-Channel 1 GS/s 8-Bit 3-Stage Capacitor Array-Assisted Charge-Injection DAC-Based SAR ADC in 28 nm CMOS

Published:2023-11-05 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE Asian Solid-State Circuits Conference (A-SSCC)
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Author:

Kye Chan-Ho¹,Choo Kyojin¹

Affiliation:

1. EPFL,Neuchâtel,Switzerland

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10347557/10347908/10347948.pdf?arnumber=10347948

Reference10 articles.

1. A 3.1mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32nm digital SOI CMOS

2. 27.3 Area-efficient 1GS/s 6b SAR ADC with charge-injection-cell-based DAC

3. 27.2 14.1-ENOB 184.9dB-FoM Capacitor-Array-Assisted Cascaded Charge-Injection SAR ADC

4. 16.5 An 8GS/s time-interleaved SAR ADC with unresolved decision detection achieving −58dBFS noise and 4GHz bandwidth in 28nm CMOS

5. An 8b 1.0-to-1.25GS/s 0.7-to-0.8V Single Stage Time-Based Gated-Ring-Oscillator ADC with 2x Interpolating Sense-Amplifier-Latches;Yonar,2023

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