A 1Mb 28nm STT-MRAM with 2.8ns read access time at 1.2V VDD using single-cap offset-cancelled sense amplifier and in-situ self-write-termination-Reference-Cited by-同舟云学术

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A 1Mb 28nm STT-MRAM with 2.8ns read access time at 1.2V VDD using single-cap offset-cancelled sense amplifier and in-situ self-write-termination

Published:2018-02 Issue: Volume: Page:
ISSN:
Container-title:2018 IEEE International Solid - State Circuits Conference - (ISSCC)
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Author:

Dong Qing,Wang Zhehong,Lim Jongyup,Zhang Yiqun,Shih Yi-Chun,Chih Yu-Der,Chang Jonathan,Blaauw David,Sylvester Dennis

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8304413/8310156/08310393.pdf?arnumber=8310393

Cited by 65 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Timing Optimization Model and PVT Tracked Scheme for STT-MRAM Voltage-Mode Sense;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-09

2. A Read Margin Enhancement Circuit With Dynamic Bias Optimization for MRAM;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-08

3. Switching characteristics of MgO-based MTJ with intermediate state;Japanese Journal of Applied Physics;2024-02-21

4. A Novel Hybrid Memory System based on Non-Volatile Memory for Edge Intelligent IoT Devices;2024 2nd International Conference on Intelligent Data Communication Technologies and Internet of Things (IDCIoT);2024-01-04

5. An 8b-Precision 8-Mb STT-MRAM Near-Memory-Compute Macro Using Weight-Feature and Input-Sparsity Aware Schemes for Energy-Efficient Edge AI Devices;IEEE Journal of Solid-State Circuits;2024-01

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