Timing Optimization Model and PVT Tracked Scheme for STT-MRAM Voltage-Mode Sense-Reference-Cited by-同舟云学术

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Timing Optimization Model and PVT Tracked Scheme for STT-MRAM Voltage-Mode Sense

Published:2024-09 Issue:9 Volume:71 Page:4019-4031
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Zhou Yongliang¹^ORCID,Lin Xiao¹,Zhou Zixuan¹^ORCID,Sun Yingxue¹,Wei Yiming¹,Yang Zhen¹,Dai Chengxing¹,Zhong JingXue¹,Wu Xiulong¹^ORCID,Peng Chunyu¹^ORCID

Affiliation:

1. School of Integrated Circuits, Anhui University, Hefei, China

Funder

Anhui Provincial Natural Science Foundation

Natural Science Foundation of the Higher Education Institutions of Anhui Province

National Natural Science Foundation of China

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx8/8919/10654306/10606069.pdf?arnumber=10606069

Reference48 articles.

1. Offset-Compensated Cross-Coupled PFET Bit-Line Conditioning and Selective Negative Bit-Line Write Assist for High-Density Low-Power SRAM

2. NOSTalgy: Near-Optimum Run-Time STT-MRAM Quality-Energy Knob Management for Approximate Computing Applications

3. ROCKY: A Robust Hybrid On-chip Memory Kit For The Processors With STT-MRAM Cache Technology

4. TA-LRW: A Replacement Policy for Error Rate Reduction in STT-MRAM Caches

5. Logic Process Compatible 40-nm 16-Mb, Embedded Perpendicular-MRAM With Hybrid-Resistance Reference, Sub-$\mu$ A Sensing Resolution, and 17.5-nS Read Access Time

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