A 7.4-to-14GHz PLL with 54fs<inf>rms</inf> jitter in 16nm FinFET for integrated RF-data-converter SoCs-Reference-Cited by-同舟云学术

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A 7.4-to-14GHz PLL with 54fsrms jitter in 16nm FinFET for integrated RF-data-converter SoCs

Published:2018-02 Issue: Volume: Page:
ISSN:
Container-title:2018 IEEE International Solid - State Circuits Conference - (ISSCC)
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Author:

Turker Didem,Bekele Ade,Upadhyaya Parag,Verbruggen Bob,Cao Ying,Ma Shaojun,Erdmann Christophe,Farley Brendan,Frans Yohan,Chang Ken

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8304413/8310156/08310342.pdf?arnumber=8310342

Cited by 64 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Analysis and Design of a Sub-Sampling PLL of Low Phase Noise and Low Reference Spur;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-08

2. A Multireference PLL: Theory and Implementation;IEEE Journal of Solid-State Circuits;2024-07

3. A 4-to-16GHz Dual-Loop PLL Based on Current-Control RO and Calibration in a 6-nm FinFET;2024 13th International Conference on Communications, Circuits and Systems (ICCCAS);2024-05-10

4. A 28.8-to-43.2 GHz 79.8 fs_rms Jitter and −78.5 dBc Reference Spur PLL Exploiting Complementary Mixing Phase Detector With Mismatch Calibration;IEEE Transactions on Microwave Theory and Techniques;2024-05

5. A 29 GHz Sub-Sampling PLL with 25.6-fs-rms RJ based on a Discrete-Time Integrating PD in 45nm RF SOI;2024 IEEE Custom Integrated Circuits Conference (CICC);2024-04-21

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