A 4-to-16GHz Dual-Loop PLL Based on Current-Control RO and Calibration in a 6-nm FinFET
Author:
Affiliation:
1. Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences,Shanghai,China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10651577/10651589/10652768.pdf?arnumber=10652768
Reference12 articles.
1. An 8.2-to-21.5 GHz Dual-Core Quad-Mode Orthogonal-Coupled VCO with Concurrently Dual-Output using Parallel 8-Shaped Resonator
2. A 7.4-to-14GHz PLL with 54fsrms jitter in 16nm FinFET for integrated RF-data-converter SoCs
3. Design and Analysis of Current Starved VCO Targeting SCL 180 nm CMOS Process
4. Analog/mixed-signal design challenges in 7-nm CMOS and beyond
5. A Family of LowPower Truly Modular Programmable Dividers in Standard 0.35m CMOS Technology
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