Circuit-Level Hardening Techniques to Mitigate Soft Errors in FinFET Logic Gates-Reference-Cited by-同舟云学术

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Circuit-Level Hardening Techniques to Mitigate Soft Errors in FinFET Logic Gates

Published:2019-09 Issue: Volume: Page:
ISSN:
Container-title:2019 19th European Conference on Radiation and Its Effects on Components and Systems (RADECS)
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Author:

Zimpeck Alexandra L.¹,Artola Laurent²,Hubert Guillaume²,Meinhardt Cristina³,Kastensmidt Fernanda L.¹,Reis Ricardo¹

Affiliation:

1. Instituto de Informatica, Universidade Federal do Rio Grande do Sul (UFRGS), PPGC/PGMicro,Porto Alegre,Brazil

2. Université de Toulouse,French Aerospace Lab (ONERA/DPHY),Toulouse,France

3. Universidade Federal de Santa Catarina (UFSC),Departamento de Informática e Estatística,Flonianópolis,Brazil

Funder

CNPq (Council of Scientific and Technologic Development)

FAPERGS (Research Support Foundation of the State of Rio Grande do Sul)

CAPES (Brazilian Coordination of Improvement of Higher-Level Personnel)

ONERA, the French Aerospace Lab

French Aerospace Lab

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9745606/9745637/09745706.pdf?arnumber=9745706

Reference23 articles.

1. Energy and Delay Tradeoffs of Soft-Error Masking for 16-nm FinFET Logic Paths: Survey and Impact of Process Variation in the Near-Threshold Region

2. Dual-Interlocked Logic for Single-Event Transient Mitigation

3. Impact of Single-Event Transient Duration and Electrical Delay at Reduced Supply Voltages on SET Mitigation Techniques

4. Single-Event Transient Modeling in a 65-nm Bulk CMOS Technology Based on Multi-Physical Approach and Electrical Simulations

5. Switch level optimization of digital CMOS gate networks

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design of high speed hybrid full adder using reversible logic gates;AIP Conference Proceedings;2024

2. Voltage Scaling Influence on the Soft Error Susceptibility of a FinFET-based Circuit;2021 IEEE 12th Latin America Symposium on Circuits and System (LASCAS);2021-02-21

3. Work-Function Fluctuation Impact on the SET Response of FinFET-based Majority Voters;2020 IEEE Latin-American Test Symposium (LATS);2020-03

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