Author:
da Rosa Leomar S.,Schneider Felipe R.,Ribas Renato P.,Reis Andre I.
Cited by
14 articles.
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3. Standard Cell and Supergates Designs: An Electrical Comparison on 4-Input Logic Functions;2022 IEEE International Symposium on Circuits and Systems (ISCAS);2022-05-28
4. Circuit Level Design Methods to Mitigate Soft Errors;2020 IEEE Latin-American Test Symposium (LATS);2020-03
5. Circuit-Level Hardening Techniques to Mitigate Soft Errors in FinFET Logic Gates;2019 19th European Conference on Radiation and Its Effects on Components and Systems (RADECS);2019-09