Component Level Reliability Evaluation of Low Cost 6-Sided Die Protection versus Wafer Level Chip Scale Packaging with 350um Ball Pitch-Reference-Cited by-同舟云学术

Component Level Reliability Evaluation of Low Cost 6-Sided Die Protection versus Wafer Level Chip Scale Packaging with 350um Ball Pitch

Published:2022-05 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)
language:
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Author:

Lim Jacinta Aman¹,Kim Byung-Cheol¹,Valencia-Gacho Rizi¹,Dunlap Brett¹

Affiliation:

1. San Diego,CA,92121

Funder

Research and Development

Publisher

IEEE

Link

Reference6 articles.

1. Fan-Out Wafer Level Packaging(FOWLP) enables Future IoT Requirements;jamshidi;MEPTEC Newsletter,2016

2. Innovative Package-on-Package Solution: M- Series™ Fan-Out (mPoP);kim;IMAPS,2021

3. Jacinta, 600mm Fan-Out on Panel Level Processing as a Scale Up Alternative to 300mm FOWLP;lim;ECTC,2021

4. Jacinta, 600mm Wafer Level Fan-Out on Panel Level Processing with 6-Sided Die Protection;lim;IWLPC,2020

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