Wafer Stacked Wide I/O DRAM with One-step TSV Technology-Reference-Cited by-同舟云学术

Wafer Stacked Wide I/O DRAM with One-step TSV Technology

Published:2022-05 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)
language:
Short-container-title:

Author:

Kawano Masaya¹,Wang Xiang-Yu¹,Ren Qin¹,Loh Woon-Leng¹,Chandra Rao B. S. S.¹,Chui King-Jien¹,Kawagoe Tsuyoshi²,Homma Ichiro²

Affiliation:

1. Institute of Microelectronics A*STAR (Agency for Science, Technology, and Research),Singapore

2. UltraMemory Inc,Stacking Process Development Department,Tokyo,Japan

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9816066/9816372/09816682.pdf?arnumber=9816682

Reference7 articles.

1. Trench Isolation Technology for Cost-effective Wafer-level 3D Integration with One-step TSV

2. New Cost-Effective Via-Last Approach by "One-Step TSV" After Wafer Stacking for 3D Memory Applications

3. Trench Isolation Technology for Cost-effective Wafer-level 3D Integration with One-step TSV;kawano;Proc 71st Electron Compon Technol Conf (ECTC),2021

4. Yield Improvement of Silicon Trench Isolation for One-Step TSV

5. Silicon Isolation Trench Integration for the 4-stack Memory Wafer

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. 3-layer Fine Pitch Cu-Cu Hybrid Bonding Demonstrator With High Density TSV For Advanced CMOS Image Sensor Applications;2024 IEEE 74th Electronic Components and Technology Conference (ECTC);2024-05-28

2. Multi Die Stacked Structure Fabricated by WoW Bonding;2023 IEEE CPMT Symposium Japan (ICSJ);2023-11-15

3. Demonstration of a Wafer Level Face- To-Back (F2B) Fine Pitch Cu-Cu Hybrid Bonding with High Density TSV for 3D Integration Applications;2023 IEEE 73rd Electronic Components and Technology Conference (ECTC);2023-05