Multi Die Stacked Structure Fabricated by WoW Bonding
Author:
Affiliation:
1. Device Technology Research Institute, National Institute of Advanced Industrial Science & Technology,Tsukuba, Ibaraki,Japan
2. UltraMemory Inc.,Stacking Process Development Department,Hachioji, Tokyo,Japan
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10339391/10339529/10339576.pdf?arnumber=10339576
Reference5 articles.
1. Electrical and Thermal Analysis of Bumpless Build Cube 3D Using Wafer-on-Wafer and Chip-on-Wafer for Near Memory Computing
2. Wafer Stacked Wide I/O DRAM with One-step TSV Technology
3. Bonding of silicon wafers for silicon‐on‐insulator
4. Warpage Reduction and Thermal Stress Study of Dicing Process in Wafer-to-Wafer Bonding Fabrication
5. 300 mm wafer-level hybrid bonding for Cu/interlayer dielectric bonding in vacuum
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